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Publié le 19 juin 2017

Journal Papers (2013 – 2016)

[1] N. Cucu Laurenciu and S.D. Cotofana, "A Nonlinear Degradation Path Dependent End-of-Life Estimation Framework from Noisy Observations”, Microelectronics Reliability, Elsevier, September 2013 [download]

[2] D. V. Nguyen and B. Vasic, “Two-bit bit flipping algorithms for LDPC codes and collective error correction”, IEEE Transactions of Communications, vol. 62, no. 4, April 2014, pp. 1153-1163 [download]

[3] S. Evain, V. Savin, V. Gherman, “Error-Correction Schemes with Erasure Information for Fast Memories”, Journal of Electronic Testing, vol. 30, no. 2, April 2014, pp. 183-192 [download]

[4] O. Al Rasheed, P. Ivanis, and B. Vasic, “Fault-Tolerant Probabilistic Gradient-Descent Bit Flipping Decoder,” IEEE Communications Letters, vol. 18, no. 9, September 2014, pp. 1487–1490 [download]

[5] S. Brkic, P. Ivanis, G. Ðordevic, B. Vasic, “Symbolic Analysis of Faulty Logic Circuits under Correlated Data-Dependent Gate Failures”, Telfor Journal, vol. 6, no. 1, November 2014, pp. 2-6 [download]

[6] O. Al Rasheed, S. Brkic, P. Ivanis, B. Vasic,, “Performance Analysis of Faulty Gallager-B Decoding of QC-LDPC Codes with Applications”, Telfor Journal, vol. 6, no. 1, November 2014, pp. 7-11 [download]

[7] C. L. Kameni Ngassa, V. Savin, E. Dupraz, D. Declercq, “Density Evolution and Functional Threshold for the Noisy Min-Sum Decoder”, IEEE Transactions on Communications, vol. 63, no. 5, May 2015, pp. 1497-1509 [download]

[8] S. Brikc, O.-A. Rasheed, P. Ivanis, and B. Vasic, "On Fault-Tolerance of the Gallager B Decoder under Data-Dependent Gate Failures," IEEE Communications Letters, vol. 19, no. 8, June 2015, pp. 1299 – 1302 [download]

[9] E. Dupraz, D. Declercq, B. Vasic, and V. Savin, “Analysis and Design of Finite Alphabet Iterative Decoders Robust to Faulty Hardware”, IEEE Transactions on Communications, vol. 63, no. 8, August 2015, pp. 2797-2809 [download]


[10] S. Brkic, P. Ivanis, and B. Vasic, "Reliability of Memories Built from Unreliable Components under Data-Dependent Gate Failures," IEEE Communications Letters, vol. 19, no. 12, October 2015, pp. 2098- 2101 [download]

[11] T. Marconi, C. Spagnol, E. Popovici, S. Cotofana, “Transmission Channel Noise Aware Energy Effective LDPC Decoding”, VLSI-SoC: Internet of Things Foundations, volume 464 of the series IFIP Advances in Information and Communication Technology, November 2015, pp. 198-219 [download]

[12] J. Chen, S. Cotofana, S. Grandhi, C. Spagnol, E. Popovici, “Inverse Gaussian distribution based timing analysis of Sub-threshold CMOS circuits”, Microelectronics Reliability, Volume 55, Issue 12, Part B, December 2015, pp. 2754-2761 [download]

[13] S. Nimara, A. Amaricai, O. Boncalo, and M. Popa, “Multi-Level Simulated Fault Injection for Data Dependent Reliability Analysis of RTL Circuit Descriptions”, Advances in Electrical and Computer Engineering, 2016 – accepted for publication [download]

[14] T. Marconi, N. Cucu Laurenciu, V. Savin, and S. Cotofana, “Energy Effective Low Complexity Counter-Based Stochastic LDPC Decoding”, IEEE Transactions on Emerging Topics in Computing

[15] S. Brkic, P. Ivanis, B. Vasic, “Reliable memories built of unreliable components: majority logic decoding and analysis of data-dependent logic gate failures", IEEE Transactions on Communications

[16] B Vasic, P. Ivanis, "Error Errore Eicitur: An Error-Correcting Error Paradigm for Reliable Information Storage on Unreliable Media," IEEE Transactions on Communications

[17] M. Lefter, T. Marconi, G.R. Voicu, S. Cotofana, "Enhanced Error Correction for 3D Polyhedral Memories", IEEE Transactions on Emerging Topics in Computing


Conference Papers (2013)

[18] C. L. Kameni Ngassa, V. Savin, D. Declercq “Design of Min-Sum-based LDPC decoders using imprecise arithmetic”, IEEE Int. Conference on Computer as a tool (EUROCON), Zagreb, Croatia, July 2013 [download]

[19] S. Brkic, P. Ivanis, G. Djordjevic, B. Vasic, “Taylor-Kuznetsov fault-tolerant memories: a survey and results under correlated gate failures“, in Proceedings of 11th International Conference on Telecommunications in Modern Satellite and Broadcasting Services (TELSIKS), Nis, Serbia, October 2013, pp. 455-461 [download]

[20] O. Al Rasheed, S. Brkic, P. Ivanis, B. Vasic, “Performance analysis of faulty Gallager B decoding of QC-LDPC Codes,” in Proceedings of 21st Telecommunication Forum (TELFOR), November 2013, Belgrade, Serbia, pp. 323-326 [download]

[21] S. Brkic, P. Ivanis, G. Djordjevic and B. Vasic “Symbolic Analysis of Faulty Logic Circuits in the Presence of Correlated Gate Failures”, in Proceedings of 21st Telecommunication Forum (TELFOR), November 2013, Belgrade, pp. 369-373 [download]

[22] C. L. Kameni Ngassa, V. Savin, D. Declercq, “Analysis of Min-Sum based Decoders Implemented on Noisy Hardware”, Asilomar Conference on Signals, Systems and Computers, Asilomar, CA, USA, November 2013 [download]

[23] C. L. Kameni Ngassa, V. Savin, D. Declercq, “Min-Sum-based decoders running on noisy hardware,” IEEE Global Communications Conference (GLOBECOM), Atlanta, GA, USA, December 2013 [download]


Conference Papers (2014)

[24] C. L. Kameni Ngassa, V. Savin, D. Declercq, “Unconventional behavior of the noisy Min-Sum decoder over the binary symmetric channel”, Information Theory and Applications Workshop (ITA), San Diego, CA, US, February 2014 [download]

[25] S. Nimara, A. Amaricai, and M. Popa, “Analysis of Transient Error Propagation in Sub-powered CMOS Circuits”, IEEE International Conf. on Microelectronics (MIEL), Belgrade, Serbia, May 2014 [download]


[26] D. McCarthy, N. Zeinolabedini, J. Chen, and E. Popovici, “Predictable, Low-power Arithmetic Logic Unit for the 8051 Microcontroller using Asynchronous Logic”, IEEE International Conference on Microelectronics (MIEL), Belgrade, Serbia, May 2014 [download]

[27] V. Savin, “LDPC Codes and Message-Passing Decoders: An Introductory Survey”, 2nd National Conference on Information Theory and Complex Systems (TINKOS), Nis, Serbia, June 2014 [download]

[28] B. Vasic and P. Ivaniš, "Reliable memories built from unreliable components: theory and connections with codes on graphs," National Conference on Information Theory and Complex Systems (TINKOS), Nis, Serbia, June 16-17, 2014 [download]

[29] B. Vasic and P. Ivaniš, "Fault-tolerant decoders," National Conference on Information Theory and Complex Systems (TINKOS), Nis, Serbia, June 16-17, 2014 [download]

[30] S. Brkic, P. Ivanis, and B. Vasic, "Analysis of one-step majority logic decoding under correlated data-dependent gate failures," in Proc. IEEE International Symposium on Information Theory (ISIT), pp. 1-5, Honolulu, USA, June 29-July 4, 2014 [download]

[31] N. Cucu Laurenciu and S. Cotofana, “Probability Density Function Based Reliability Evaluation of Large-Scale ICs”, ACM/IEEE International Symposium on Nanoscale Architectures (NANOARCH), Paris, France, July 2014 [download]


[32] J. Chen, C. Spagnol, S. Grandhi, E. Popovici, S. Cotofana, and A.  Amaricai, “Linear Compositional Delay Model for the Timing Analysis of Sub-Powered Combinational Circuits”, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Tampa, Florida, USA, July 2014 [download]

[33] S. Nimara, A. Amaricai, O. Boncalo, and M. Popa “Probabilistic saboteur-based simulated fault injection techniques for low supply voltage interconnects”, 10th Conference on PhD Research in Microelectronics (PRIME), Grenoble, France, July 2014 [download]

[34] S. Grandhi, C. Spagnol, E. Popovici, "Reliability analysis of logic circuits using probabilistic techniques," 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), Grenoble, France, July 2014 [download]

[35] S. K.  Planjery, D.  Declercq, M.  Diouf,  and B. Vasic, "On the guaranteed error-correction of decimation-enhanced iterative decoding for column-weight-three codes," 8th International  Symposium  on Turbo Codes and Iterative Information  Processing (ISTC), Bremen, Germany, August 2014 [download]

[36] C.L. Kameni Ngassa, V. Savin, and D. Declercq, “Faulty Stochastic LDPC Decoders over the Binary Symmetric Channel”, IEEE International Symposium on Turbo Codes and Iterative Information Processing (ISTC), Bremen, Germany, August 2014 [download]

[37] E. Dupraz, D. Declercq, B. Vasic, and V. Savin, “Finite Alphabet Iterative Decoders Robust to Faulty Hardware: Analysis and Selection”, 8th International Symposium on Turbo Codes and Iterative Information Processing (ISTC), Bremen, Germany, August 2014 [download]

[38] A. Amaricai, S. Nimara, O. Boncalo, J. Chen, and E. Popovici, “Probabilistic Gate Level Fault Modeling for Near and Sub-Threshold CMOS Circuits”, 17th Euromicro Conference on Digital System Design (DSD), Verona, Italy, August 2014 [download]


[39] O. Boncalo, A. Amaricai, A. Hera, and V. Savin, “Cost-efficient FPGA layered LDPC decoder with serial AP-LLR processing”, 24th International Conference on Field Programmable Logic and Applications (FPL), Munchen, Germany, September 2014 [download]

[40] J. Chen, A. Tisserand, E. Popovici and S. Cotofana, “Robust Sub-powered Asynchronous Logic”, IEEE International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS),  Palma de Mallorca, Spain, September 2014 [download]

[41] S. Grandhi, C. Spagnol,  J. Chen, E. Popovici, S. Cotafona, "Reliability aware logic synthesis through rewriting," in Proc. of IEEE International System-on-Chip Conference (SOCC),  Las Vegas, NV, September 2014, pp.274-279 [download]

[42] V. Ilic, E. Dupraz, D. Declercq and B. Vasic, "Uniformly Reweighted APP Decoder for Memory Efficient Decoding of LDPC Codes", in Proc. 52nd Annual Allerton Conference on Communication, Control, and Computing (Allerton), Allerton House, Illinois, USA, October 2014 [download]

[43] T. Marconi, C. Spagnol, E. Popovici and S. Cotofana,"Towards Energy Effective LDPC Decoding by Exploiting Channel Noise Variability", IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Playa del Carmen, Mexico, October 2014 [download]

[44] O. Boncalo, A. Amaricai, C. Spagnol, and E. Popovici, “Cost effective FPGA probabilistic fault emulation”, 32nd NORCHIP Conference, Tampere, Finland, October 2014 [download]


Conference Papers (2015)

[45] E. Dupraz, D. Declercq, and B. Vasic, “Analysis of Taylor-Kuznetsov Memory using One-Step Majority Logic Decoder”, Information Theory and Applications Workshop (ITA), San Diego, CA, US, February 2015 [download]

[46] B. Vasic, P. Ivanis, S. Brkic, and V. Ravanmehr, "Fault-Resilient Decoders and Memories made of Unreliable Components " In Proceedings of Information Theory and Applications Workshop (ITA), San Diego, CA, February 2015 [download]

[47] I. Mot, A. Amaricai, and O. Boncalo “Performance Enhancement of Serial Based FPGA Probabilistic Fault Emulation Techniques” Proc. IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Belgrade, April 2015 [download]

[48] S. Nimara, A. Amaricai, and M. Popa “Sub-threshold CMOS circuits reliability assessment using simulated fault injection based on simulator commands” Proc. IEEE International Symposium on Applied Computational Intelligence (SACI), Timisoara, May 2015 [download]

[49] Elsa Dupraz, David Declercq, “Evaluation of the Robustness of LDPC Encoders to Hardware Noise”, IEEE International Black Sea Conference on Communications and Networking (BlackSeaCom), Constanta, Romania, May 2015 [download]

[50] J. Chen, A. Tisserand, E. Popovici, S. Cotofana, "Asynchronous Charge Sharing Power Consistent Montgomery Multiplier," IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), Mountain View, CA, May 2015, pp. 132-138 [download]

[51] K. Le, D. Declercq, F. Ghaffari, C. Spagnol, E. Popovici, P. Ivanis, and B. Vasic, “Efficient Realization Of Probabilistic Gradient Descent Bit Flipping Decoders”, International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, May 2015 [download]

[52] T. Marconi and S. Cotofana, “Dynamic Bitstream Length Scaling Energy Effective Stochastic LDPC Decoding”, ACM Great Lakes Symposium on VLSI (GLSVLSI), Pittsburgh, Pennsylvania, USA, May 2015 [download]


[53] P. Ivanis, O. Al Rasheed, and B. Vasic, “MUDRI: A fault-tolerant decoding algorithm”, in IEEE International Conference on Communications (ICC), London, June 2015, pp. 1-6 [download]

[54] E. Dupraz, D. Declercq, S. Ouya, and B. Vasic, "Stabilité des Mémoires de Taylor-Kuznetsov construites à partir d’un décodeur LDPC de type Gallager B," XXVe Colloque GRETSI - Traitement du Signal et des Images, Lyon, France, September 2015, pp.1079-1083 [download]

[55] F. Pater, A. Amaricai “Probability Density Function Modeling for Sub-Powered Interconnects” Proc. International Conference on Numerical Analysis and Applied Mathematics (INCAAM), Rhodes, September 2015 [download]

[56] B. Vasic, S. Brkic, and P. Ivanis, “Low Complexity Memory Architectures Based on LDPC Codes: Benefits and Disadvantages,” Proc. 12th International Conference on Telecommunications in Modern Satellite, Cable and Broadcasting Services (TELSIKS), Nis, Serbia, October 2015, pp. 11-18 [download]

[57] S. Grandhi, D. McCarthy, C, Spagnol, E. Popovici, S. Cotofana, "ROST-C: Reliability driven optimisation and synthesis techniques for combinational circuits," IEEE International Conference on Computer Design (ICCD), New York, NY, October 2015, pp.431-434 [download]

[58] A. Amaricai, V. Savin, O. Boncalo, N. Cucu-Laurenciu, J. Chen, and S. Cotofana “Timing error analysis of flooded LDPC decoders” Proc. IEEE Conference on Microwave, Communication, Antennas and Electronic Systems (COMCAS), Tel Aviv, November 2015 [download]


[59] A. Amaricai, O. Boncalo, and I. Mot “Memory efficient FPGA implementation for flooded LDPC decoder”, Telecommunication Forum Conference (TELFOR), Belgrade, November 2015 [download]

[60] A. Amaricai, N. Cucu-Laurenciu, O. Boncalo, J. Chen, S. Nimara, V. Savin, S. Cotofana “Multi-Level Probabilistic Timing Error Reliability Analysis Using a Circuit Dependent Fault Map Generation”, Proc. 30th Conference on Design of Circuits and Integrated Systems (DCIS), Estoril, November 2015 [download]


Conference Papers (2016)

[61] S. Brkic, P. Ivanis, B. Vasic, and D. Declercq, “Message-Aggregation Enhanced Iterative Hard-Decision Decoders,” Information Theory and Applications Workshop (ITA), San Diego, CA, February 2016, pp. 1-10 [download]

[62] B. Vasic, P. Ivanis, and D. Declercq, “Approaching Maximum Likelihood Performance of LDPC Codes by Stochastic Resonance in Noisy Iterative Decoders,” Information Theory and Applications Workshop (ITA), San Diego, CA, February 2016 [download]

[63] E. Dupraz, V. Savin, S. Grandhi, E. Popovici, and D. Declercq, “Practical LDPC Encoders Robust to Hardware Errors”, IEEE International Conference on Communications (ICC), Kuala Lumpur, Malaysia, May 2016 [download]

[64] S. Grandhi, E. Dupraz, C. Spagnol, V. Savin, E. Popovici, “CPE: Codeword Prediction Encoder”, IEEE European Test Symposium accepted (ETS), Amsterdam, The Netherlands, May 2016 [download]

[65] S. Nimara, O. Boncalo, A. Amaricai, M. Popa “FPGA Architecture of Multi-Codeword LDPC Decoder with Efficient BRAM Utilization” IEEE International Symposium On Design and Diagnostics of Electronic Circuits and Systems (DDECS), Kosice, Slovakia, April 2016

[66] S. Brkic, P. Ivaniš, B. Vasic, D. Declercq, “Guaranteed Error Correction of Faulty Bit-Flipping Decoders under Data-Dependent Gate Failures,” Proc. IEEE International Symposium on Information Theory (ISIT), Barcelona, Spain, July 2016

[67] P. Ivaniš, B. Vasic, D. Declercq, “Performance Evaluation of Faulty Iterative Decoders using Absorbing Markov Chains,” Proc. IEEE International Symposium on Information Theory (ISIT), Barcelona, Spain, July 2016

[68] N. Cucu Laurenciu, S.D. Cotofana, "Haar-based Interconnect Coding for Energy Effective, Reliable Data Transport", Design Automation Conference (DAC), Austin, TX, June 2016