The i-RISC workshop is intended to be an interaction forum for information and coding theory, circuits and systems, computer engineering, and communication systems researchers, whose research goals aim to advance knowledge and understanding of reliable computing systems built from unreliable components. In this line of reasoning we invite presentation proposals. Example relevant topics (both theoretical and experimental) of interest include (but are not limited to):
- > Error models and energy measurement tools for sub-powered CMOS circuits
- > Analysis and design of error correcting codes operating on unreliable (noisy) hardware
- > Reliable data storage and interconnects through the use of error correcting codes
- > Reliable evaluation of Boolean functions with unreliable components
A one page abstract should be sent by e-mail to Valentin Savin and/or to Sorin Cotofana. As the workshop in meant to be a domain cross-fertilization agora, where researchers from different domains can exchange ideas and inspire each other, no full papers are expected from the contributors. Thus the presented results can be further improved and included in future conference or journal papers. The slides of the accepted presentations will be made available to the attendants on memory sticks on PDF format.
Deadline: July 21, 2013
Registration |
A 100 € registration fee is required for the non ESSCIRC/ESSDERC 2013 registered attendants (see ESSCIRC 2013) |