Error Models and Energy Measures
The project proposed accurate probabilistic fault models for CMOS circuits operating at very low power supply voltage values, based on a Dynamic Timing Analysis (DTA). Two analytical methods for reliability analysis of probabilistic circuits have been developed. The first one relies on an Inverse Gaussian (IG) distribution delay model, which allows accurate and fast reliability evaluation of probabilistic circuits. The second method employs a Markov chain based symbolic analysis methodology, which takes into account data dependencies. Markov chains have been used to describe both input and output dependent error models. Moreover, a variable reduction method has also been developed, in order to analyze gate net-lists composed of basic logic gates.
In order to address the reliability assessment of logic circuits represented by gate-level net-lists, the project also started developing the gate level simulated fault injection methodology. Existing Hardware Description Languages (HDL) based Simulated Fault Injection (SFI) frameworks and methodologies have been extended, so as to accommodate data dependent probabilistic errors. The proposed SFI methodology can accommodate different gate-level fault models and is targeted on the reliability estimation of gate-level net-lists generated during the logic synthesis process.
Fault Tolerant Algorithms for Error Correction
The project has further investigated noisy versions of several LDPC decoders: the finite precision Min-Sum (MS) decoder, a modified version of the MS decoder incorporating a dynamical correction of mis-convergence, called self-corrected MS (SC-MS), and more general decoders based on non-linear Boolean function for the message passing updates, called Finite Alphabet Iterative Decoders (FAID). Theoretical limits for the MS and FAID decoders under faulty hardware have been derived by using a noisy Density Evolution (DE) approach. The project has also focused on means to improve the decoder reliability, by protecting critical bits of the finite-precision computation flow within the decoding process. To this end, sign-preserving error models have been investigated, and their benefits have been demonstrated asymptotically through DE analysis, and verified at finite-lengths by Monte Carlo simulations.
Additionally, the project has also conducted a finite length statistical analysis of the different decoders. In particular, the noisy SC-MS decoder has been shown to provide nearly the same performance as the noiseless decoder, for a wide range of values of the hardware noise parameters. For FAID decoders, it has been shown that one can identify message passing update rules which are naturally more robust to transient errors, and more importantly, that the best update rules for the noisy case are not the same as the best update rules for the noiseless case.
Reliable Data Storage and Transport
The project has further investigated the design of fault-tolerant Taylor-Kuznetsov (TK) memory architectures based on structured LDPC codes. The influence of different code parameters, decoder structures and fault model parameters on the overall system performance has also been studied. A novel class of two-bit bit flipping (TBF) algorithms has been proposed, showing a significant improvement of the bit error rate performance, as compared to traditional bit flipping algorithms. The TBF decoder failures have been characterized by constructing the trapping set profile of the decoder, and it has been shown that different TBF decoders are capable of correcting different error patterns. The explicit construction of trapping set profiles allows rigorous selections of multiple TBF algorithms that can collectively correct a fixed number of errors with high probability.
As fast decoding convergence is an important issue for fault tolerant memories, the project has also proposed a novel class of fast convergence iterative decoders called decimation-enhanced FAIDs. The proposed technique is based on deactivating a carefully chosen number of nodes from the computation tree, which speed up the decoding process, while maintaining the same error correction performance. Furthermore, it has been proved that guaranteed error-correction could be achieved in a finite and small number of iterations. This represents a first result on guaranteed error-correction for advanced message-passing decoders, and hopefully will allow designing TK-memory architectures with guaranteed robustness properties.
Reliable Boolean Function Synthesis
The project has further focused on data structures and design flow for the systematic synthesis of reliable circuits. A number of data structures have been analyzed and the And-Inverter-Graph (AIG) structure has been identified as the most appropriate for the project goals, due to its compactness, versatility to incorporate many parameters of concern, and scalability to any circuit size. Based on the selected data structure, a first version of an i-RISC tool for computing the reliability of a circuit was implemented. This tool was further integrated within a Verilog/VHDL Hardware Description Language based design flow, combining custom and academic tools with more established/industry accepted tools, in order to allow evaluation and validation of the project designs at various levels. Moreover, the project has also introduced a Probability Density Functions (PDFs) based Integrated Circuit (IC) reliability assessment framework, which employs a distribution of probabilities for a closer adherence to a faulty circuit stochastic behavior. The proposed framework, which takes an unorthodox approach towards reliability estimation, yields a fast and scalable reliability assessment approach, to be integrated in reliability aware synthesis tools.
Finally, the project has also started investigations related to the systematic synthesis of fault tolerant combinational circuits, though the concept of error correction driven graph augmentation. A number of circuit classes were identified and a first analysis into the encoding of such circuits was performed.