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Publié le 7 juin 2017

​Proposed Approach

Error correcting codes utilization proved to be a fundamental information theory cornerstone, providing an efficient solution to the problem of reliable communication over unreliable channels. The i-RISC project is aimed at shifting the error correction paradigm from communication to computing systems. The central i-RISC target is to acquire error-free computing with error-prone components. i-RISC proposes to tackle this problem by detouring error correcting codes from their traditional use, such that they provide efficient protection against circuit-induced errors. To make such an approach viable, both fundamental and exploratory research must be conducted at different circuit or system levels.

A first level of research is required to characterize and optimize the circuit probabilistic behavior. The goal is to develop error models that cover the effects of chip sub-powering, production imperfections, environmental deterioration, and aging. Moreover it is necessary to analyze the effect of energy consumption, clock frequency, environmental condition, and area requirements on the circuit error probability.

A second level of research is required to advance the knowledge and understanding of error-correcting codes in the context of unreliable devices. In contrast to the traditional use of error correcting codes, faulty hardware represents a new error source that can perturb the encoding and/or decoding process. It is then crucial to analyze and design error correcting encoders and decoders able to provide reliable error correction even if they are made out of unreliable components.

A third level of research is required to investigate the design of fault tolerant error correction techniques that can contribute to the reliable storage and transfer of the digital information throughout the chip. This relies on the well-known principle of encoded information processing, but the codec must be made compliant with the requirements of reliable interconnects and memories.

A fourth level of research is required to identify solutions that allow combining the codec architecture with the hardware it protects. i-RISC will study potential links between graph representations of digital circuits and of error correcting codes, in order to generate fault tolerant implementation of the circuit logical functionality.

The above research levels are strongly interacting and eventually converge to an effective fault-tolerance solution, which allows circuit multi-objective optimization, with respect to size, energy consumption, latency, and reliability. The optimization is taking into account the design of the fault-tolerant decoder architecture, its integration into the structural description of the circuit, and the unreliable component error models. Finally, the effectiveness of the proposed solutions will be demonstrated through the implementation of fault tolerant decoders and of a number of benchmark circuits.