Innovative Reliable Chip Designs from Low-Powered Unreliable Components
i-RISC is a FET-OPEN project funded by the European Commission under the Seventh Framework Programme (Grant Agreement number 309129)
i-RISC Workshop on Innovative Reliable Chip Designs from Unreliable Components, European Solid-State Circuits Conference (ESSCIRC), Bucharest, Romania, September 20, 2013
i-RISC Workshop “When Boole Meets Shannon”, George Boole’s Bicentenary Celebrations, Cork, Ireland, September 1-2, 2015
The on-going miniaturization of data processing and storage devices and the low-energy consumption imperative can only be sustained through low-powered components. However, lower supply voltages combined with the intrinsic device variations introduced by emerging nanoelectronic device fabrication process make them inherently unreliable. As a consequence, the nanoscale integration of reliable chips built out of unreliable components emerged as one of the most critical challenges for the next-generation electronic circuit design. To make such nanoscale integration economically viable, new solutions for efficient fault-tolerant data processing and storage must be investigated.
The i-RISC project targets a foundational breakthrough towards reliable, fault-tolerant chip design from unreliable components, which is a crucial issue for the computing technology long-term development. The research novelty emerges from the synergistic utilization of (1) information theory and coding techniques, traditionally utilized to improve the communication systems reliability and (2) circuit and system theory and design techniques, in order to create reliable/ predictable hardware. The aim is to enable the development of innovative fault-tolerant solutions at both circuit- and system-level that are fundamentally rooted in mathematical models, algorithms, and techniques from information and coding theory.
Error correcting codes utilization proved to be a fundamental cornerstone of information theory, providing an efficient solution to the problem of reliable communication over unreliable channels. The i-RISC project is aimed at shifting the error correction paradigm from communication to computing systems. The central i-RISC target is to acquire error-free computing with error-prone components. i-RISC proposes to tackle this problem by detouring error correcting codes from their traditional use, such that they provide efficient protection against circuit-induced errors. To make such an approach viable, both fundamental and exploratory research must be conducted at different circuit or system levels.
The i-RISC project acts as a pathfinder, which in the long term may lead to completely new and revolutionary solutions for the next-generation low-power electronic circuit design, through the reliable nanoscale integration of chips built out of unreliable components. By the end of the project, we intend to evaluate the potential implications of the proposed approach in real-life scenarios. To this end, proofs of concept are envisaged for key i-RISC approach items and to demonstrate how specific results can be integrated such that a reliable processor can be constructed out of unreliable components.
We believe that the successful demonstration of i-RISC’s goal of applying concepts of modern coding theory to the development of novel fault-tolerant devices will provide a new measure of performance in memory and computing systems. Although the primary targeted technology is CMOS, the proposed techniques may be adapted and applied to post-CMOS technologies. In addition to the technical merit of improved system performance, it will also serve as a framework for research in these fields.
The expected technological impact of the i-RISC project can greatly influence the design optimization and the energy efficiency of future electronic circuits, contributing significantly to the evolution of the ICT infrastructure in the Europe and abroad. New coding techniques can improve the performance of memory and computing systems without requiring major improvements in (the physical reliability of) materials and devices. The i-RISC project is seen by the consortium’s members as one of the most viable paths to continue the life of Moore’s law. On a broader scale the results of this work will have a direct impact on the performance capabilities of new generation of memories, computers, and electronic devices, thus benefiting to the society as a whole.
Start Date : 01/02/2013End Date : 31/01/2016Total Cost : 2.161.095 €Funding : 1.613.284 €Estimated Effort: 274 PMCall identifier: FP7-ICT-2011-C
Description of the Work - Year 1
New ElectronicsSilicon RepublicIndustrie & Technologies
Dr. Valentin SavinProject coordinatorCEA-LETI, MINATEC Campus17 rue des MartyrsF-38054 GRENOBLE, Cedex 9Phone: + 33 (0)438 780 963E-mail:firstname.lastname@example.org
Acteur majeur de la recherche, du développement et de l'innovation, le CEA intervient dans quatre grands domaines : énergies bas carbone, défense et sécurité, technologies pour l’information et technologies pour la santé.