i-RISC Workshop on Innovative Reliable Chip Designs from Unreliable Components, European Solid-State Circuits Conference (ESSCIRC), Bucharest, Romania, September 20, 2013
V. Savin and S. Cotofana, “Innovative Reliable Chip Designs from Low-Powered Unreliable Components”, i-RISC Workshop, European Solid-State Circuits Conference (ESSCIRC), Bucharest, Romania, September 20, 2013 [download]
C. L. Kameni Ngassa, V. Savin, and D. Declercq, “Analysis and Design of Min-Sum-based Decoders Running on Noisy Hardware”, i-RISC Workshop, European Solid-State Circuits Conference (ESSCIRC), Bucharest, Romania, September 20, 2013 [download]
D. Declercq, S. Planjery, and B. Vasic, “Performance of Finite Alphabet Iterative Decoders (FAID) Under Faulty Hardware”, i-RISC Workshop, European Solid-State Circuits Conference (ESSCIRC), Bucharest, Romania, September 20, 2013
B. Vasic, S. Brkic, P. Ivanis, and G. Djordjevic, “Bit-flipping Decoders for Fault-Tolerant Memories”, i-RISC Workshop, European Solid-State Circuits Conference (ESSCIRC), Bucharest, Romania, September 20, 2013
S. Brkic, P. Ivanis, G. Djordjevic, B. Vasic, “The analysis of Taylor-Kuznetsov fault-tolerant memories under correlated gate failures“, i-RISC Workshop, European Solid-State Circuits Conference (ESSCIRC), Bucharest, Romania, September 20, 2013 [download]
S. Nimara, A. Amaricai, O Boncalo, J. Chen, and E. Popovici, “Gate Level Simulated Fault Injection for Probabilistic CMOS Circuits”, i-RISC Workshop, European Solid-State Circuits Conference (ESSCIRC), Bucharest, Romania, September 20, 2013 [download]
A. Amaricai, O Boncalo, and S. Nimara, “Interconnect Crosstalk Analysis in Sub-powered Integrated Circuits”, i-RISC Workshop, European Solid-State Circuits Conference (ESSCIRC), Bucharest, Romania, September 20, 2013 [download]
J. Chen, C. Spagnol, S. Kumar, and E. Popovici, “Delay Relevant Reliability of CMOS Circuits”, i-RISC Workshop, European Solid-State Circuits Conference (ESSCIRC), Bucharest, Romania, September 20, 2013 [download]
C. Spagnol, S. Kumar, J. Chen, and E. Popovici, “A systematic Approach for Reliability Evaluation of Combinational Circuits”, i-RISC Workshop, European Solid-State Circuits Conference (ESSCIRC), Bucharest, Romania, September 20, 2013
N. Cucu-Laurenciu, and S. Cotofana, “Reliability Assessment Framework for Large Scale Causal Logic Networks”, i-RISC Workshop, European Solid-State Circuits Conference (ESSCIRC), Bucharest, Romania, September 20, 2013 [download]
i-RISC Workshop “When Boole Meets Shannon”, George Boole’s Bicentenary Celebrations, Cork, Ireland, September 1-2, 2015
V. Savin, “Reliable Computing with Unreliable Components: An Error Correcting based Approach”, 2nd i-RISC Workshop, “When Boole Meets Shannon”, Cork, Ireland, September 2015
B. Vasic , P. Ivanis , D. Declercq , K. LeTrung , E. Dupraz, “Iterative Decoders with Deliberate Message Flips”, 2nd i-RISC Workshop, “When Boole Meets Shannon”, Cork, Ireland, September 2015 [download]
E. Dupraz, S. K. Grandhi, V. Savin, E. Popovici, D. Declercq, “Reliable LDPC Encoding on Faulty Hardware”, 2nd i-RISC Workshop, “When Boole Meets Shannon”, Cork, Ireland, September 2015 [download]
S. Grandhi, “A EDA framework for reliability driven synthesis”, 2nd i-RISC Workshop, “When Boole Meets Shannon”, Cork, Ireland, September 2015 [download]
A. Amaricai, O. Boncalo, S. Nimara, N. Cucu-Laurenciu, J. Chen, V. Savin, and S. Cotofana, “A Simulated Fault Injection Analysis of Flooded LDPC Decoders”, 2nd i-RISC Workshop, “When Boole Meets Shannon”, Cork, Ireland, September 2015 [download]
S. Cotofana, “Is Boole’s Computation Avenue Getting Bumpy?”, 2nd i-RISC Workshop, “When Boole Meets Shannon”, Cork, Ireland, September 2015 [download]
N. Cucu-Laurenciu and S.D. Cotofana, “Energy Effective Reliable Data Transport”, 2nd i-RISC Workshop, “When Boole Meets Shannon”, Cork, Ireland, September 2015
K. Le, F. Ghaffari, D. Declercq, “Efficient Hardware Implementation of Probabilistic Gradient Descent Bit Flipping Algorithm”, 2nd i-RISC Workshop, “When Boole Meets Shannon”, Cork, Ireland, September 2015 [download]
Other Seminar/Workshop Presentations
S. Cotofana, “Lifetime Reliability Aware Resource Management and Computing: Challenges & Opportunities”, FETCH Winter School, Leysin, Switzerland, January 2013 [download]
C. L. Kameni Ngassa, V. Savin, and D. Declercq, “Min-Sum-based decoders running on noisy hardware”, Groupement de Recherche – Information, Signal, Image et Vision (GdR-ISIS), Telecom ParisTech, Paris, July 2, 2013 [download]
E. Popovici, “Systematic Power Estimation and Optimisation for Deep Submicron Digital ICs”, CAIRN Seminars, INRIA, Rennes July 2013
A. Amaricai, “iRISC – Innovative Reliable Chip Designs from Low-Powered Unreliable Components”, joint HiPEAC-HuRo Workshop, Timisoara, February 12, 2014
S. Grandhi, C. Spagnol, J. Chen, D. McCarthy and E. Popovici, “i-RISC: Innovative Reliable Chip Designs from Low-Powered Unreliable Components”, “Workshop on Designing with Uncertainty - Opportunities & Challenges, PAnDA project, York, UK, March 18, 2014
O. Boncalo, A. Amaricai, and V. Savin, “Cost efficient FPGA implementations of Min-Sum and Self-Corrected-Min-Sum decoders”, Journée inter-GDR SoCSiP & ISIS : Architectures de Codes Correcteurs d'Erreurs, Télécom Bretagne, Brest, November 4, 2014
E. Dupraz, D. Declercq, B. Vasic, and V. Savin, “Finite Alphabet Iterative Decoders Robust to Faulty Hardware”, Groupement de Recherche – Information, Signal, Image et Vision (GDR-ISIS), Jussieu, Paris, November 19, 2014 [download]
V. Savin, “Energy-Efficient Computing: A Coding Theory Perspective”, Workshop on Energy-Efficient Computing Systems, Dynamic Adaptation of Quality of Service and Approximate Computing, HiPEAC & EC, Fondation Universitaire, Brussels, November 27, 2014