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i-RISC Workshop on Innovative Reliable Chip Designs from Unreliable Components

​The Workshop will be collocated with the 39th European Solid-State Circuits Conference (ESSCIRC), which will be held in Bucarest from 16 to 20 September, 2013.
Organizers: Valentin Savin (CEA-LETI, France) and Sorin Cotofana (TU Delft, The Netherlands)

Workshop Program & Presentations

Publié le 7 juin 2017

Context

The ongoing miniaturization of data processing and storage devices and the imperative of low-energy consumption can only be sustained through low-powered components. However, lower supply voltages combined with variations in technological process of emerging nanoelectronic devices make them inherently unreliable. As a consequence, the nanoscale integration of chips built out of unreliable components has emerged as one of the most critical challenges for the next-generation electronic circuit design. To make such nanoscale integration economically viable, new solutions for efficient and fault-tolerant data processing and storage must be investigated.

 

Workshop Purpose

The i-RISC Workshop addresses the problem of reliable computing with unreliable components, which is a crucial issue for the long-term development of computing technology. The Workshop main goal is to explore the synergistic utilization of information and coding theory and techniques, traditionally utilized to improve the reliability of communication systems, and circuit and system theory and design techniques in order to create reliable/predictable hardware. The aim is to enable the development of innovative fault-tolerant solutions at both circuit- and system-level that are fundamentally rooted in mathematical models, algorithms, and techniques of information and coding theory

 

Call for Contributions

The i-RISC workshop is intended to be an interaction forum for information and coding theory, circuits and systems, computer engineering, and communication systems researchers, whose research goals aim to advance knowledge and understanding of reliable computing systems built from unreliable components. In this line of reasoning we invite presentation proposals. Example relevant topics (both theoretical and experimental) of interest include (but are not limited to):

  • > Error models and energy measurement tools for sub-powered CMOS circuits
  • > Analysis and design of error correcting codes operating on unreliable (noisy) hardware
  • > Reliable data storage and interconnects through the use of error correcting codes
  • > Reliable evaluation of Boolean functions with unreliable components

A one page abstract should be sent by e-mail to Valentin Savin and/or to Sorin Cotofana. As the workshop in meant to be a domain cross-fertilization agora, where researchers from different domains can exchange ideas and inspire each other, no full papers are expected from the contributors. Thus the presented results can be further improved and included in future conference or journal papers. The slides of the accepted presentations will be made available to the attendants on memory sticks on PDF format.

Deadline: July 21, 2013

 

Registration

A 100 € registration fee is required for the non ESSCIRC/ESSDERC 2013 registered attendants (see ESSCIRC 2013)
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Call for Contributions

Deadline: July 21, 2013.


 

Workshop Program

Download as PDF file