Expected Final Results and Their Potential Impact and Use
The i-RISC project acts as a pathfinder, which in the long term may lead to completely new and revolutionary solutions for the next-generation low-power electronic circuit design, through the reliable nanoscale integration of chips built out of unreliable components. By the end of the project, we intend to evaluate the potential implications of the proposed approach in real-life scenarios. To this end, proofs of concept are envisaged for key i-RISC approach items and to demonstrate how specific results can be integrated such that a reliable processor can be constructed out of unreliable components.
We believe that the successful demonstration of i-RISC’s goal of applying concepts of modern coding theory to the development of novel fault-tolerant devices will provide a new measure of performance in memory and computing systems. Although the primary targeted technology is CMOS, the proposed techniques may be adapted and applied to post-CMOS technologies. In addition to the technical merit of improved system performance, it will also serve as a framework for research in these fields.
The expected technological impact of the i-RISC project can greatly influence the design optimization and the energy efficiency of future electronic circuits, contributing significantly to the evolution of the ICT infrastructure in the Europe and abroad. New coding techniques can improve the performance of memory and computing systems without requiring major improvements in (the physical reliability of) materials and devices. The i-RISC project is seen by the consortium’s members as one of the most viable paths to continue the life of Moore’s law. On a broader scale the results of this work will have a direct impact on the performance capabilities of new generation of memories, computers, and electronic devices, thus benefiting to the society as a whole.